This invention relates to a semiconductor device and to a method of manufacturing a semiconductor device.
U.S. Pat. No. 4,003,072 describes a semiconductor device comprising a semiconductor body having a first device region of one conductivity type forming with a second device region of the opposite conductivity type provided adjacent one of the major surfaces of the semiconductor body a first pn junction which is reverse-biassed in at least one mode of operation of the device, and a floating further region of the opposite conductivity type provided within the first device region remote from the major surfaces of the semiconductor body and spaced from the second device region so that, in the one mode of operation of the device, the depletion region of the first pn junction reaches the floating further region before the first pn junction breaks down.
Such a device is shown in, for example, FIG. 5 of U.S. Pat. No. 4,003,072 where an array of floating further regions is provided. The floating further regions act to increase the voltage at which the device breaks down when the first pn junction is reverse-biassed in operation of the device. Thus, when under such reverse-biassing conditions the first region is depleted of free charge carriers, the ionized impurity atoms in the further floating regions act to divert electric field lines from the oppositely charged ionized impurity atoms in the first device region. These electric field lines would otherwise serve to increase the field at the first pn junction and help to cause breakdown at the first pn junction. However, because of the tendency of the pn junction(s) between the floating further region(s) and the first device region to become forward-biassed, which reduces the potential between the second device region and the floating region and may cause the potential of the floating region to become fixed, it is difficult for high electric fields to exist above the floating further region(s). This adversely affects the reverse breakdown voltages which can be attained.